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vishay siliconix dg411hs, dg412hs, dg413hs document number: 72053 s13-1283-rev. d, 27-may-13 www.vishay.com 1 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com precision monolithic quad spst cmos analog switches description the dg411hs series of monolithic quad analog switches was designed to provide high speed, low error switching of precision analog signals. combining low power (0.35 w) with high speed (t on : 68 ns), the dg411hs family is ideally suited for portable and battery powered industrial and military applications. to achieve high-voltage ratings and superior switching performance, the dg411hs se ries was built on vishay siliconix?s high voltage silico n gate process. an epitaxial layer prevents latchup. each switch conducts equally well in both directions when on, and blocks input voltages up to the supply levels when off. the dg411hs and dg412hs respond to opposite control logic as shown in the truth table. the dg413hs has two normally open and two normally closed switches. features ? 44 v supply max. rating ? 15 v analog signal range ? on-resistance - r ds(on) : 25 ? ? fast switching - t on : 68 ns ? ultra low power - p d : 0.35 w ? ttl, cmos compatible ? single supply capability benefits ? widest dynamic range ? low signal rrro rs and distortion ? break-before-make switching action ? simple interfacing applications ? precision automatic test equipment ? precision data acquisition ? communication systems ? battery powered systems ? computer peripherals functional block diagram and pin configuration * pb containing terminations are not rohs compliant, exemptions may apply top view s 2 v+ v l s 3 in 3 d 3 d 4 in 4 in 2 d 2 d 1 in 1 s 1 v- gnd s 4 1 2 3 4 5 6 8 7 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 top view in 1 in 2 d 1 d 2 s 1 s 2 v- v+ gnd v l s 4 s 3 d 4 d 3 in 4 in 3 dual-in-line and soic to p view s 1 s 2 v- v+ nc nc gnd v l s 4 s 3 lcc nc in 3 d 3 d 4 in 4 nc in 2 d 2 d 1 in 1 key 910111213 4 5 6 7 8 1 2 319 20 14 15 16 17 18 dg411hs dg411hs dg411hs qfn16 truth table logic dg411hs dg412hs 0onoff 1offon a v aila b le a v aila b le
vishay siliconix dg411hs, dg412hs, dg413hs www.vishay.com 2 document number: 72053 s13-1283-rev. d, 27-may-13 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com functional block diagram and pin configuration top view s 1 s 2 v- v+ nc nc gnd v l s 4 s 3 lcc nc in 3 d 3 d 4 in 4 nc in 2 d 2 d 1 in 1 key 910111213 4 5 6 7 8 1 2 319 20 14 15 16 17 18 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 top view in 1 in 2 d 1 d 2 s 1 s 2 v- v+ gnd v l s 4 s 3 d 4 d 3 in 4 in 3 dual-in-line and soic dg413hs dg413hs top view s 2 v+ v l s 3 in 3 d 3 d 4 in 4 in 2 d 2 d 1 in 1 s 1 v- gnd s 4 1 2 3 4 5 6 8 7 16 15 14 13 12 11 10 9 dg413hs qfn16 truth table logic sw 1 , sw 4 sw 2 , sw 3 0offon 1onoff ordering information temp. range package part number dg411hs, dg412hs - 40 c to 85 c 16-pin plastic dip dg411hsdj dg411hsdj-e3 dg412hsdj dg412hsdj-e3 16-pin narrow soic dg411hsdy dg411hsdy-e3 dg411hsdy-t1 dg411hsdy-t1-e3 dg412hsdy dg412hsdy-e3 dg412hsdy-t1 dg412hsdy-t1-e3 16-pin qfn 4 x 4 mm (variation 1) dg411hsdn-t1-e4 dg412hsdn-t1-e4 dg413hs - 40 c to 85 c 16-pin plastic dip dg413hsdj dg413hsdj-e3 16-pin narrow soic dg413hsdy dg413hsdy-e3 dg413hsdy-t1 dg413hsdy-t1-e3 16-pin qfn 4 x 4 mm (variation 1) dg413hsdn-t1-e4
vishay siliconix dg411hs, dg412hs, dg413hs document number: 72053 s13-1283-rev. d, 27-may-13 www.vishay.com 3 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com notes: a. signals on s x , d x , or in x exceeding v+ or v- will be clamped by internal diodes. limit forward di ode current to maximum current ratings. b. all leads welded or soldered to pc board. c. derate 6 mw/c above 25 c. d. derate 7.6 mw/c above 75 c. e. derate 12 mw/c above 75 c. f. derate 23.5 mw/c above 70 c. absolute maximum ratings parameter limit unit v+ to v- 44 v gnd to v- 25 v l (gnd - 0.3) to (v+) + 0.3 digital inputs a , v s , v d (v-) - 2 to (v+) + 2 or 30 ma, whichever occurs first continuous current (any terminal) 30 ma peak current, s or d (pulsed 1 ms, 10 % duty cycle) 100 storage temperature (ak, az suffix) - 65 to 150 c (dj, dy, dn suffix) - 65 to 125 power dissipation (package) b 16-pin plastic dip c 470 mw 16-pin narrow soic d 600 16-pin cerdip e 900 lcc-20 e 900 16-pin (4 x 4 mm) qfn f 1880 specifications a parameter symbol test conditions unless specified v+ = 15 v, v- = - 15 v v l = 5 v, v in = 2.4 v, 0.8 v f temp. b typ. c a suffix - 55 c to 125 c d suffix - 40 c to 85 c unit min. d max. d min. d max. d analog switch analog signal range e v analog full - 15 15 - 15 15 v drain-source on-resistance r ds(on) v+ = 13.5 v, v- = - 13.5 v i s = - 10 ma, v d = 8.5 v room full 25 35 45 35 45 ? switch off leakage current i s(off) v+ = 16.5 v, v- = - 16.5 v v d = 15.5 ma, v s = 15.5 v room full 0.1 - 0.25 - 20 0.25 20 - 0.25 - 5 0.25 5 na i d(off) room full 0.1 - 0.25 - 20 0.25 20 - 0.25 - 5 0.25 5 channel on leakage current i d(on) v+ = 16.5 v, v- = - 16.5 v v d = v s = 15.5 v room full 0.1 - 0.4 - 40 0.4 40 - 0.4 - 10 0.4 10 digital control input current, v in low i il v in under test = 0.8 v full 0.005 - 0.5 0.5 - 0.5 0.5 a input current, v in high i ih v in under test = 2.4 v full 0.005 - 0.5 0.5 - 0.5 0.5 input capacitance e c in f = 1 mhz room 5 pf dynamic characteristics tu r n - o n t i m e t on r l = 300 ? , c l = 35 pf v s = 10 v, see figure 2 room full 68 105 127 105 116 ns turn-off time t off room full 42 80 94 80 90 break-before-make time delay t d dg413hs only, v s = 10 v r l = 300 ? , c l = 35 pf room 20 charge injection e qv g = 0 v, r g = 0 ? , c l = 10 nf room 22 pc
vishay siliconix dg411hs, dg412hs, dg413hs www.vishay.com 4 document number: 72053 s13-1283-rev. d, 27-may-13 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com notes: a. refer to process option flowchart. b. room = 25 c, full = as determin ed by the operating temperature suffix. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. the algebraic convention whereby the most negative value is a minimum and the most pos itive a maximum, is used in this data sheet. e. guaranteed by design, not subject to production test. f. v in = input voltage to perform proper function. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. specifications a parameter symbol test conditions unless specified v+ = 15 v, v- = - 15 v v l = 5 v, v in = 2.4 v, 0.8 v f temp. b typ. c a suffix - 55 c to 125 c d suffix - 40 c to 85 c unit min. d max. d min. d max. d dynamic characteristics (cont?d) off isolation e oirr r l = 50 ? , c l = 5 pf f = 1 mhz room - 91 db channel-to-channel crosstalk e x ta l k room - 88 source off capacitance e c s(off) f = 1 mhz room 12 pf drain off capacitance e c d(off) room 12 channel on capacitance e c d(on) room 30 power supplies positive supply current i+ v+ = 16.5 v, v- = - 16.5 v v in = 0 or 5 v room full 0.0001 1 5 1 5 a negative supply current i- room full - 0.0001 - 1 - 5 - 1 - 5 logic supply current i l room full 0.0001 1 5 1 5 ground current i gnd room full - 0.0001 - 1 - 5 - 1 - 5 specifications a (for unipolar supplies) parameter symbol test conditions unless specified v+ = 12 v, v- = 0 v v l = 5 v, v in = 2.4 v, 0.8 v f temp. b typ. c a suffix - 55 c to 125 c d suffix - 40 c to 85 c unit min. d max. d min. d max. d analog switch analog signal range e v analog full 12 12 v drain-source on-resistance r ds(on) v+ = 10.8 v, i s = - 10 ma v d = 3 v, 8 v room full 49 80 100 80 100 ? dynamic characteristics tu r n - o n t i m e t on r l = 300 ? , c l = 35 pf v s = 8 v, see figure 2 room hot 95 140 180 140 160 ns turn-off time t off room hot 36 70 79 70 74 break-before-make time delay t d dg413hs only, v s = 8 v r l = 300 ? , c l = 35 pf room 60 charge injection q v g = 6 v, r g = 0 ? , c l = 1 nf room 60 pc power supplies positive supply current i+ v+ = 13.2 v, v in = 0 or 5 v room hot 0.0001 1 5 1 5 a negative supply current i- room hot - 0.0001 - 1 - 5 - 1 - 5 logic supply current i l room hot 0.0001 1 5 1 5 ground current i gnd room hot - 0.0001 - 1 - 5 - 1 - 5
vishay siliconix dg411hs, dg412hs, dg413hs document number: 72053 s13-1283-rev. d, 27-may-13 www.vishay.com 5 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com typical characteristics (25 c, unless otherwise noted) on-resistance vs. v d and dual supply voltage leakage current vs. analog voltage on-resistance vs. v d and temperature v d - drain voltage (v) 5 15 25 35 45 55 65 - 20 - 15 - 10 - 5 0 5 10 15 20 t a = 25 c 5 v 8 v 10 v 12 v 15 v 20 v r ds(on) - drain-source on-resistance ( ) - 100 - 75 - 50 - 25 0 25 50 - 15 -10 - 5 0 5 10 15 v d or v s - drain or source voltage (v) v+ = + 5 v v - = - 15 v v l = 5 v i d(off) i s(off) i d(on) i s , i d (pa) 5 15 25 35 45 55 65 75 024681012 v d - drain voltage (v) r ds(on) - drain-source on-resistance ( ) v+ = 12 v v - = 0 v v l = 5 v 125 c - 55 c 25 c 85 c on-resistance vs. v d and unipolar supply voltage on-resistance vs. v d and temperature insertion loss, off-is olation, crosstalk vs. frequency 0 50 100 150 200 250 300 02468101214161820 t a = 25 c v l = 5 v v d - drain voltage (v) v+ = 3.0 v v l = 3 v v+ = 5.0 v v+ = 8.0 v v+ = 12.0 v v+ = 15.0 v v+ = 20.0 v r ds(on) - drain-source on-resistance ( ) 5 10 15 20 25 30 35 40 45 - 15 - 10 - 5 0 5 10 15 v+ = 15 v v - = - 15 v v l = 5 v 125 c 85 c 25 c - 55 c v d - drain voltage (v) r ds(on) - drain-source on-resistance ( ) 110 v+ = 15 v v - = - 15 v v l = 5 v r l = 50 oirr x talk 100 k 1 m frequency (hz) loss 10 m 100 m 1 g loss, oirr, x tlak (db) 0 0 - 10 - 20 - 40 - 70 - 60 - 50 - 80 - 90 - 100 - - 30
vishay siliconix dg411hs, dg412hs, dg413hs www.vishay.com 6 document number: 72053 s13-1283-rev. d, 27-may-13 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com typical characteristics (25 c, unless otherwise noted) charge injection vs. analog voltage switching time vs. temperature - 100 - 80 - 60 - 40 - 20 0 20 40 60 80 100 - 15 - 10 - 5 0 5 10 15 v - drain voltage (v) v = 15 v v = 12 v q - charge injection (pc) 20 40 60 80 100 120 140 - 55 - 35 - 15 5 25 45 65 85 105 125 t on/ t off (ns) v+ = 15 v v - = - 15 v v l = 5 v t on t off temperature ( c) charge injection vs. analog voltage switching time vs. temperature - 100 - 80 - 60 - 40 - 20 0 20 40 60 80 100 - 15 - 10 - 5 0 5 10 15 v s - source voltage (v) v = 15 v v = 12 v q - charge injection (pc) 20 40 60 80 100 120 140 - 55 - 35 - 15 5 25 45 65 85 105 125 t on/ t off (ns) v+ = 12 v v - = 0 v v l = 5 v t on t off temperature ( c) supply current vs. input switching frequency f - frequency (hz) i supply 100 ma 10 ma 1 ma 100 a 10 a 1 a 100 na 10 na 100 1 k 10 k 100 k 1 m 10 m i+, i - i l v+ = 15 v v - = - 15 v v l = 5 v = 1 sw = 4 sw 10
vishay siliconix dg411hs, dg412hs, dg413hs document number: 72053 s13-1283-rev. d, 27-may-13 www.vishay.com 7 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com schematic diagram (typical channel) test circuits figure 1. level shift/ drive v in v l s v+ gnd v- d v- v+ figure 2. switching time 0 v logic input switch input* 3 v 50 % 0 v v s t r < 5 ns t f < 5 ns 90 % t off t on v o note: logic input waveform is inverted for switches that have the opposite logic sense control c l (includes fixture and stray capacitance) v+ in r l r l + r ds(on) v o = v s sd - 15 v v o gnd 10 v v l c l 35 pf v- r l 300 + 15 v + 5 v 90 % figure 3. break-before-make (dg413hs) 0 v logic input switch switch output 3 v 50 % 0 v output 0 v 90 % v o2 v o1 90 % v s1 v s2 t d t d v o2 c l (includes fixture and stray capacitance) v+ s 2 v- s 1 v l v s2 in 2 d 2 v s1 r l2 300 d 1 v o1 c l2 35 pf -15 v gnd + 5 v + 15 v r l1 300 c l1 35 pf in 1
vishay siliconix dg411hs, dg412hs, dg413hs www.vishay.com 8 document number: 72053 s13-1283-rev. d, 27-may-13 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com test circuits vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?72053 . figure 4. charge injection c l 1 nf d r g v o v+ s v- 3 v in v l v g -15 v gnd + 15 v + 5 v off on off off on off v o v o in x in x q = v o x c l figure 5. crosstalk 0 v, 2.4 v s 1 x talk isolation = 20 log v o v s d 2 c = rf bypass r l d 1 s 2 v s 0 v, 2.4 v in 1 50 v o in 2 r g = 50 v l v+ - 15 v gnd v - nc c + 15 v c + 5 v c figure 6. off-isolation r l 50 d 0 v, 2.4 v v+ r g = 50 -15 v gnd v- c v s off isolation = 20 log v o v s in v l v o + 5 v c + 15 v s c c = rf bypass figure 7. source/drain capacitances d in s v l v+ -15 v gnd v - c 0 v, 2.4 v meter hp4192a impedance analyzer or equivalent + 5 v c + 15 v c
all leads 0.101 mm 0.004 in e h c d e b a1 l 4 3 12 8 7 56 13 14 16 15 9 10 12 11 package information vishay siliconix document number: 71194 02-jul-01 www.vishay.com 1
jedec part number: ms-012 dim min max min max a 1.35 1.75 0.053 0.069 a 1 0.10 0.20 0.004 0.008 b 0.38 0.51 0.015 0.020 c 0.18 0.23 0.007 0.009 d 9.80 10.00 0.385 0.393 e 3.80 4.00 0.149 0.157 e 1.27 bsc 0.050 bsc h 5.80 6.20 0.228 0.244 l 0.50 0.93 0.020 0.037 0 8 0 8 ecn: s-03946?rev. f, 09-jul-01 dwg: 5300
e 1 e q 1 a l a 1 e 1 b b 1 s c e a d 15 max 12345678 16 15 14 13 12 11 10 9 package information vishay siliconix document number: 71261 06-jul-01 www.vishay.com 1

dim min max min max a 3.81 5.08 0.150 0.200 a 1 0.38 1.27 0.015 0.050 b 0.38 0.51 0.015 0.020 b 1 0.89 1.65 0.035 0.065 c 0.20 0.30 0.008 0.012 d 18.93 21.33 0.745 0.840 e 7.62 8.26 0.300 0.325 e 1 5.59 7.11 0.220 0.280 e 1 2.29 2.79 0.090 0.110 e a 7.37 7.87 0.290 0.310 l 2.79 3.81 0.110 0.150 q 1 1.27 2.03 0.050 0.080 s 0.38 1.52 .015 0.060 ecn: s-03946?rev. d, 09-jul-01 dwg: 5482
e 1 e q 1 a l a 1 e 1 b b 1 l 1 s c e a d 12 3 4 5 6 7 8 16 15 14 13 12 11 10 9 package information vishay siliconix document number: 71282 03-jul-01 www.vishay.com 1
dim min max min max a 4.06 5.08 0.160 0.200 a 1 0.51 1.14 0.020 0.045 b 0.38 0.51 0.015 0.020 b 1 1.14 1.65 0.045 0.065 c 0.20 0.30 0.008 0.012 d 19.05 19.56 0.750 0.770 e 7.62 8.26 0.300 0.325 e 1 6.60 7.62 0.260 0.300 e 1 2.54 bsc 0.100 bsc e a 7.62 bsc 0.300 bsc l 3.18 3.81 0.125 0.150 l 1 3.81 5.08 0.150 0.200 q 1 1.27 2.16 0.050 0.085 s 0.38 1.14 0.015 0.045 0 15 0 15 ecn: s-03946?rev. g, 09-jul-01 dwg: 5403
d l 1 e b l e a 1 a 28 1 2 packaging information vishay siliconix document number: 71290 02-jul-01 www.vishay.com 1

dim min max min max 1.37 2.24 0.054 0.088 1.63 2.54 0.064 0.100 0.56 0.71 0.022 0.028 8.69 9.09 0.342 0.358 8.69 9.09 0.442 0.358 1.27 bsc 0.050 bsc 1.14 1.40 0.045 0.055 1.96 2.36 0.077 0.093 ecn: s-03946?rev. b, 09-jul-01 dwg: 5321
package information www.vishay.com vishay siliconix revision: 22-apr-13 1 document number: 71921 for technical questions, contact: powerictechsuppo rt@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 qfn 4x4-16l case outline notes (1) use millimeters as the primary measurement. (2) dimensioning and tole rances conform to asme y14.5m. - 1994. (3) n is the number of terminals. nd and ne is the number of terminals in each d and e site respectively. (4) dimensions b applies to plated terminal and is measured betwee n 0.15 mm and 0.30 mm from terminal tip. (5) the pin 1 identifier must be existed on the top surface of the package by using identification mark or other feature of package body. (6) package warpage max. 0.05 mm. variation 1 variation 2 dim millimeters (1) inches millimeters (1) inches min. nom. max. min. nom. max. min. nom. max. min. nom. max. a 0.75 0.85 0.95 0.029 0.033 0.037 0.75 0.85 0.95 0.029 0.033 0.037 a1 0 - 0.05 0 - 0.002 0 - 0.05 0 - 0.002 a3 0.20 ref. 0.008 ref. 0.20 ref. 0.008 ref. b 0.25 0.30 0.35 0.010 0.012 0.014 0.25 0.30 0.35 0.010 0.012 0.014 d 4.00 bsc 0.157 bsc 4.00 bsc 0.157 bsc d2 2.0 2.1 2.2 0.079 0.083 0.087 2.5 2.6 2.7 0.098 0.102 0.106 e 0.65 bsc 0.026 bsc 0.65 bsc 0.026 bsc e 4.00 bsc 0.157 bsc 4.00 bsc 0.157 bsc e2 2.0 2.1 2.2 0.079 0.083 0.087 2.5 2.6 2.7 0.098 0.102 0.106 k 0.20 min. 0.008 min. 0.20 min. 0.008 min. l 0.5 0.6 0.7 0.020 0.024 0.028 0.3 0.4 0.5 0.012 0.016 0.020 n (3) 16 16 16 16 nd (3) 4444 ne (3) 4444 ecn: s13-0893-rev. b, 22-apr-13 dwg: 5890 (4) (5)
application note 826 vishay siliconix www.vishay.com document number: 72608 24 revision: 21-jan-08 application note recommended minimum pads for so-16 recommended minimum pads for so-16 0.246 (6.248) recommended mi nimum pads dimensions in inches/(mm) 0.152 (3.861) 0.047 (1.194) 0.028 (0.711) 0.050 (1.270) 0.022 (0.559) 0.372 (9.449) return to index return to index
vishay siliconix an505 document number: 74976 19-apr-07 www.vishay.com 1 recommended minimum pads for qfn-16 (4 x 4 mm body) note: qfn-16 (4 x 4) has an exposed center pad that must not come into contact with any metalized structure on the pcb. this area is considered a keep out zone. inches millimeters c1 0.142 3.60 c2 0.142 3.60 e 0.026 0.65 x1 0.014 0.35 x2 0.089 2.25 y1 0.037 0.95 y2 0.089 2.25 1 2 3 4 12 11 10 9 16 15 14 1 3 5 6 7 8 keep o u t zone c1 x2 x1 e y1 c2 y2
legal disclaimer notice www.vishay.com vishay revision: 02-oct-12 1 document number: 91000 disclaimer all product, product specifications and data are subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employee s, and all persons acting on it s or their behalf (collectivel y, vishay), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, repres entation or guarantee regarding the suitabilit y of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicable law, vi shay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation specia l, consequential or incidental damages, and (iii) any and all i mplied warranties, including warra nties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of products for certain type s of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in generic applications. such statements are not binding statements about the suitability of products for a particular application. it is the customers responsib ility to validate that a particu lar product with the properties descri bed in the product specification is suitable fo r use in a particular application. parameters provided in datasheets and/or specification s may vary in different applications an d performance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vish ays terms and condit ions of purchase, including but not limited to the warranty expressed therein. except as expressly indicate d in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vi shay product could result in personal injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk. pleas e contact authorized vishay personnel to ob tain written terms and conditions regarding products designed for such applications. no license, express or implied, by estoppel or otherwise, to any intellectual prope rty rights is granted by this document or by any conduct of vishay. product names and markings noted herein may be trad emarks of their respective owners. material category policy vishay intertechnology, inc. hereby certi fies that all its products that are id entified as rohs-compliant fulfill the definitions and restrictions defined under directive 2011/65/eu of the euro pean parliament and of the council of june 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (eee) - recast, unless otherwis e specified as non-compliant. please note that some vishay documentation may still make reference to rohs directive 2002/95/ ec. we confirm that all the products identified as being compliant to directive 2002 /95/ec conform to directive 2011/65/eu. vishay intertechnology, inc. hereby certifi es that all its products that are identified as ha logen-free follow halogen-free requirements as per jedec js709a stan dards. please note that some vishay documentation may still make reference to the iec 61249-2-21 definition. we co nfirm that all the products identified as being compliant to iec 61249-2-21 conform to jedec js709a standards.

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